#include <irq.h>
#include <util.h>
#include <arch/cpu/soc/irqs.h>

#define S3C2440_EXTINT_LOWLEV    (0x00)
#define S3C2440_EXTINT_HILEV     (0x01)
#define S3C2440_EXTINT_FALLEDGE  (0x02)
#define S3C2440_EXTINT_RISEEDGE  (0x04)
#define S3C2440_EXTINT_BOTHEDGE  (0x06)

static void s3c_irq_mask(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);
	struct s3c2440_interrupt *interrupt = s3c2440_get_base_interrupt();
    unsigned int irqno = desc->irq - IRQ_EINT0;
    unsigned int mask;

    mask = readl(&interrupt->intmask);
    mask |= 1 << irqno;
    writel(mask, &interrupt->intmask);
}

static void s3c_irq_ack(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);
	struct s3c2440_interrupt *interrupt = s3c2440_get_base_interrupt();
    unsigned int bitval = 1 << (desc->irq - IRQ_EINT0);

    writel(bitval, &interrupt->srcpnd);
    writel(bitval, &interrupt->intpnd);
}

static void s3c_irq_maskack(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);
	struct s3c2440_interrupt *interrupt = s3c2440_get_base_interrupt();
    unsigned int bitval = 1 << (data->irq - IRQ_EINT0);
    unsigned int mask;

    mask = readl(&interrupt->intmask);
    writel(mask | bitval, &interrupt->intmask);

    writel(bitval, &interrupt->srcpnd);
    writel(bitval, &interrupt->intpnd);
}

static void s3c_irq_unmask(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);
	struct s3c2440_interrupt *interrupt = s3c2440_get_base_interrupt();
	unsigned int irqno = desc->irq - IRQ_EINT0;
    unsigned int mask;

	mask  = readl(&interrupt->intmask);
    mask &= ~(1 << irqno);
	writel(mask, &interrupt->intmask);
}

static struct irq_chip s3c_irq_level_chip = {
    .name       = "s3c-level",
    .irq_ack    = s3c_irq_maskack,
    .irq_mask   = s3c_irq_mask,
    .irq_unmask = s3c_irq_unmask,
};

static struct irq_chip s3c_irq_chip = {
    .name       = "s3c",
    .irq_ack    = s3c_irq_ack,
    .irq_mask   = s3c_irq_mask,
    .irq_unmask = s3c_irq_unmask,
};

static void s3c_irqext_mask(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);
	struct s3c2440_gpio *gpio = s3c2440_get_base_gpio();
	unsigned int irqno = desc->irq - IRQ_EINT4 + 4;
    unsigned int mask;

    mask  = readl(&gpio->eintmask);
    mask |= (1 << irqno);
    writel(mask, &gpio->eintmask);
}

static void s3c_irqext_ack(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);
	struct s3c2440_gpio *gpio = s3c2440_get_base_gpio();
	unsigned int irqno = desc->irq - IRQ_EINT4 + 4;
    unsigned int bit = 1 << irqno;
    unsigned int req;
    unsigned int mask;

    mask = readl(&gpio->eintmask);
    writel(bit, &gpio->eintpend);
    req = readl(&gpio->eintpend);
    req &= ~mask;

    /* not sure if we should be acking the parent irq... */

    if (desc->irq <= IRQ_EINT7) {
        if ((req & 0xf0) == 0) {
			struct s3c2440_interrupt *interrupt = s3c2440_get_base_interrupt();
			unsigned int bitval = 1 << (IRQ_EINT4t7 - IRQ_EINT0);

			writel(bitval, &interrupt->srcpnd);
			writel(bitval, &interrupt->intpnd);
		}
    } else {
        if ((req >> 8) == 0) {
			struct s3c2440_interrupt *interrupt = s3c2440_get_base_interrupt();
			unsigned int bitval = 1 << (IRQ_EINT8t23 - IRQ_EINT0);

			writel(bitval, &interrupt->srcpnd);
			writel(bitval, &interrupt->intpnd);
		}
    }
}

static void s3c_irqext_unmask(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);
	struct s3c2440_gpio *gpio = s3c2440_get_base_gpio();
	unsigned int irqno = desc->irq - IRQ_EINT4 + 4;
    unsigned int mask;

    mask = readl(&gpio->eintmask);
    mask &= ~(1 << irqno);
    writel(mask, &gpio->eintmask);
}

static int s3c_irqext_type(struct irq_chip *chip, unsigned int type)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);
	struct s3c2440_gpio *gpio = s3c2440_get_base_gpio();
    void *extint_reg;
    void *gpcon_reg;
    unsigned int gpcon_offset, extint_offset;
    unsigned int newvalue = 0, value;

	if ((desc->irq >= IRQ_EINT0) && (desc->irq <= IRQ_EINT3)) {
        gpcon_reg = &gpio->gpfcon;
        extint_reg = &gpio->extint[0];
        gpcon_offset = (desc->irq - IRQ_EINT0) * 2;
        extint_offset = (desc->irq - IRQ_EINT0) * 4;
    } else if ((desc->irq >= IRQ_EINT4) && (desc->irq <= IRQ_EINT7)) {
        gpcon_reg = &gpio->gpfcon;
        extint_reg = &gpio->extint[0];
        gpcon_offset = (desc->irq - IRQ_EINT4 + 4) * 2;
        extint_offset = (desc->irq - IRQ_EINT4 + 4) * 4;
    } else if ((desc->irq >= IRQ_EINT8) && (desc->irq <= IRQ_EINT15)) {
        gpcon_reg = &gpio->gpgcon;
        extint_reg = &gpio->extint[1];
        gpcon_offset = (desc->irq - IRQ_EINT8) * 2;
        extint_offset = (desc->irq - IRQ_EINT8) * 4;
    } else if ((data->irq >= IRQ_EINT16) && (data->irq <= IRQ_EINT23)) {
        gpcon_reg = &gpio->gpgcon;
        extint_reg = &gpio->extint[2];
        gpcon_offset = (desc->irq - IRQ_EINT8) * 2;
        extint_offset = (desc->irq - IRQ_EINT16) * 4;
    } else {
        return -1;
    }

    /* Set the GPIO to external interrupt mode */
    value = readl(gpcon_reg);
    value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
    writel(value, gpcon_reg);

    /* Set the external interrupt to pointed trigger type */
    switch (type)
    {
        case IRQ_TYPE_EDGE_RISING:
            newvalue = S3C2440_EXTINT_RISEEDGE;
            break;

        case IRQ_TYPE_EDGE_FALLING:
            newvalue = S3C2440_EXTINT_FALLEDGE;
            break;

        case IRQ_TYPE_EDGE_BOTH:
            newvalue = S3C2440_EXTINT_BOTHEDGE;
            break;

        case IRQ_TYPE_LEVEL_LOW:
            newvalue = S3C2440_EXTINT_LOWLEV;
            break;

        case IRQ_TYPE_LEVEL_HIGH:
            newvalue = S3C2440_EXTINT_HILEV;
            break;

        default:
            return -EINVAL;
    }

    value = readl(extint_reg);
    value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
    writel(value, extint_reg);

    return 0;
}

static struct irq_chip s3c_irqext_chip = {
    .name       = "s3c-ext",
    .irq_mask   = s3c_irqext_mask,
    .irq_unmask = s3c_irqext_unmask,
    .irq_ack    = s3c_irqext_ack,
    .irq_set_type   = s3c_irqext_type,
};

static struct irq_chip s3c_irq_eint0t3 = {
    .name       = "s3c-ext0t3",
    .irq_ack    = s3c_irq_ack,
    .irq_mask   = s3c_irq_mask,
    .irq_unmask = s3c_irq_unmask,
    .irq_set_type   = s3c_irqext_type,
};

static inline void s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit, int subcheck)
{
	struct s3c2440_interrupt *interrupt = s3c2440_get_base_interrupt();
    unsigned int mask;
    unsigned int submask;

    submask = readl(&interrupt->intsubmsk);
    mask = readl(&interrupt->intmsk);

    submask |= (1 << (irqno - IRQ_RX0));

    /* check to see if we need to mask the parent IRQ */

    if ((submask  & subcheck) == subcheck)
        writel(mask | parentbit, &interrupt->intmsk);

    /* write back masks */
    writel(submask, &interrupt->intsubmsk);
}

static inline void s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
{
	struct s3c2440_interrupt *interrupt = s3c2440_get_base_interrupt();
    unsigned int mask;
    unsigned int submask;

    submask = readl(&interrupt->intsubmsk);
    mask = readl(&interrupt->intmsk);

    submask &= ~(1 << (irqno - IRQ_RX0));
    mask &= ~parentbit;

    /* write back masks */
    writel(submask, &interrupt->intsubmsk);
    writel(mask, &interrupt->intmsk);
}

static inline void s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
{
	struct s3c2440_interrupt *interrupt = s3c2440_get_base_interrupt();
    unsigned int bit = 1 << (irqno - IRQ_RX0);

    s3c_irqsub_mask(irqno, parentmask, group);

    writel(bit, &interrupt->subsrcpnd);

    /* only ack parent if we've got all the irqs (seems we must
     * ack, all and hope that the irq system retriggers ok when
     * the interrupt goes off again)
     */
	writel(parentmask, &interrupt->srcpnd);
	writel(parentmask, &interrupt->intpnd);
}

static inline void s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
{
	struct s3c2440_interrupt *interrupt = s3c2440_get_base_interrupt();
    unsigned int bit = 1 << (irqno - IRQ_RX0);

    writel(bit, &interrupt->subsrcpnd);

    /* only ack parent if we've got all the irqs (seems we must
     * ack, all and hope that the irq system retriggers ok when
     * the interrupt goes off again)
     */
	writel(parentmask, &interrupt->srcpnd);
	writel(parentmask, &interrupt->intpnd);
}

#define INTMSK_UART0     (1 << (IRQ_UART0 - IRQ_EINT0))
#define INTMSK_UART1     (1 << (IRQ_UART1 - IRQ_EINT0))
#define INTMSK_UART2     (1 << (IRQ_UART2 - IRQ_EINT0))
#define INTMSK_ADC		 (1 << (IRQ_ADC - IRQ_EINT0))

/* UART0 */

static void s3c_irq_uart0_mask(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);

    s3c_irqsub_mask(desc->irq, INTMSK_UART0, 7);
}

static void s3c_irq_uart0_unmask(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);

    s3c_irqsub_unmask(desc->irq, INTMSK_UART0);
}

static void s3c_irq_uart0_ack(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);

    s3c_irqsub_maskack(desc->irq, INTMSK_UART0, 7);
}

static struct irq_chip s3c_irq_uart0 = {
    .name       = "s3c-uart0",
    .irq_mask   = s3c_irq_uart0_mask,
    .irq_unmask = s3c_irq_uart0_unmask,
    .irq_ack    = s3c_irq_uart0_ack,
};

/* UART1 */

static void s3c_irq_uart1_mask(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);

    s3c_irqsub_mask(desc->irq, INTMSK_UART1, 7 << 3);
}

static void s3c_irq_uart1_unmask(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);

    s3c_irqsub_unmask(desc->irq, INTMSK_UART1);
}

static void s3c_irq_uart1_ack(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);

    s3c_irqsub_maskack(desc->irq, INTMSK_UART1, 7 << 3);
}

static struct irq_chip s3c_irq_uart1 = {
    .name       = "s3c-uart1",
    .irq_mask   = s3c_irq_uart1_mask,
    .irq_unmask = s3c_irq_uart1_unmask,
    .irq_ack    = s3c_irq_uart1_ack,
};

/* UART2 */

static void s3c_irq_uart2_mask(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);

    s3c_irqsub_mask(desc->irq, INTMSK_UART2, 7 << 6);
}

static void s3c_irq_uart2_unmask(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);

    s3c_irqsub_unmask(desc->irq, INTMSK_UART2);
}

static void s3c_irq_uart2_ack(struct irq_data *data)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);

    s3c_irqsub_maskack(desc->irq, INTMSK_UART2, 7 << 6);
}

static struct irq_chip s3c_irq_uart2 = {
    .name       = "s3c-uart2",
    .irq_mask   = s3c_irq_uart2_mask,
    .irq_unmask = s3c_irq_uart2_unmask,
    .irq_ack    = s3c_irq_uart2_ack,
};

/* ADC and Touchscreen */

static void s3c_irq_adc_mask(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);

    s3c_irqsub_mask(desc->irq, INTMSK_ADC, 3 << 9);
}

static void s3c_irq_adc_unmask(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);

    s3c_irqsub_unmask(desc->irq, INTMSK_ADC);
}

static void s3c_irq_adc_ack(struct irq_chip *chip)
{
	struct irq_desc *desc = container_of(chip, struct irq_desc, chip);

    s3c_irqsub_ack(desc->irq, INTMSK_ADC, 3 << 9);
}

static struct irq_chip s3c_irq_adc = {
    .name       = "s3c-adc",
    .irq_mask   = s3c_irq_adc_mask,
    .irq_unmask = s3c_irq_adc_unmask,
    .irq_ack    = s3c_irq_adc_ack,
};

/* irq demux for adc */
static void s3c_irq_demux_adc(unsigned int irq, struct irq_desc *desc)
{
	struct s3c2440_interrupt *interrupt = s3c2440_get_base_interrupt();
    unsigned int subsrc, submsk;
    unsigned int offset = 9;

    /* read the current pending interrupts, and the mask
     * for what it is available */

    subsrc = readl(&interrupt->subsrcpnd);
    submsk = readl(&interrupt->intsubmsk);

    subsrc &= ~submsk;
    subsrc >>= offset;
    subsrc &= 3;

    if (subsrc != 0) {
        if (subsrc & 1) {
            generic_handle_irq(IRQ_TC);
        }
        if (subsrc & 2) {
            generic_handle_irq(IRQ_ADC);
        }
    }
}

static void s3c_irq_demux_uart(unsigned int start)
{
	struct s3c2440_interrupt *interrupt = s3c2440_get_base_interrupt();
    unsigned int subsrc, submsk;
    unsigned int offset = start - IRQ_RX0;

    /* read the current pending interrupts, and the mask
     * for what it is available */

	subsrc = readl(&interrupt->subsrcpnd);
	submsk = readl(&interrupt->intsubmsk);

    subsrc &= ~submsk;
    subsrc >>= offset;
    subsrc &= 7;

    if (subsrc != 0) {
        if (subsrc & 1)
            generic_handle_irq(start);

        if (subsrc & 2)
            generic_handle_irq(start + 1);

        if (subsrc & 4)
            generic_handle_irq(start + 2);
    }
}

/* uart demux entry points */

static void s3c_irq_demux_uart0(unsigned int irq, struct irq_desc *desc)
{
    s3c_irq_demux_uart(IRQ_RX0);
}

static void s3c_irq_demux_uart1(unsigned int irq, struct irq_desc *desc)
{
    s3c_irq_demux_uart(IRQ_RX1);
}

static void s3c_irq_demux_uart2(unsigned int irq, struct irq_desc *desc)
{
    s3c_irq_demux_uart(IRQ_RX2);
}

static void s3c_irq_demux_extint8(unsigned int irq, struct irq_desc *desc)
{
	struct s3c2440_gpio *gpio = s3c2440_get_base_gpio();
    unsigned int eintpnd = readl(&gpio->eintpend);
    unsigned int eintmsk = readl(&gpio->eintmask);

	eintpnd &= ~eintmsk;
	eintpnd &= ~0xff;   /* ignore lower irqs */

    /* we may as well handle all the pending IRQs here */

    while (eintpnd) {
        irq = ffs(eintpnd);
        eintpnd &= ~(1 << irq);

        irq += (IRQ_EINT4 - 4);
        generic_handle_irq(irq);
    }

}

static void s3c_irq_demux_extint4t7(unsigned int irq, struct irq_desc *desc)
{
	struct s3c2440_gpio *gpio = s3c2440_get_base_gpio();
    unsigned int eintpnd = readl(&gpio->eintpend);
    unsigned int eintmsk = readl(&gpio->eintmask);

    eintpnd &= ~eintmsk;
    eintpnd &= 0xff;    /* only lower irqs */

    /* we may as well handle all the pending IRQs here */

    while (eintpnd) {
        irq = ffs(eintpnd);
        eintpnd &= ~(1 << irq);

        irq += (IRQ_EINT4 - 4);

        generic_handle_irq(irq);
    }
}

void s3c2440_init_irq(void)
{
	struct s3c2440_gpio *gpio = s3c2440_get_base_gpio();
	struct s3c2440_interrupt *interrupt = s3c2440_get_base_interrupt();
    unsigned int pend;
    unsigned int last;
    unsigned int irqno, i;

    /* first, clear all interrupts pending... */

    last = 0;
    for (i = 0; i < 4; i++) {
        pend = readl(&gpio->eintpend);

        if (pend == 0 || pend == last)
            break;

        writel(pend, &gpio->eintpend);
        last = pend;
    }

    last = 0;
    for (i = 0; i < 4; i++) {
        pend = readl(&interrupt->intpnd);

        if (pend == 0 || pend == last)
            break;

        writel(pend, &interrupt->srcpnd);
        writel(pend, &interrupt->intpnd);
        last = pend;
    }

    last = 0;
    for (i = 0; i < 4; i++) {
        pend = readl(&interrupt->subsrcpnd);

        if (pend == 0 || pend == last)
            break;

        writel(pend, &interrupt->subsrcpnd);
        last = pend;
    }

    /* register the main interrupts */

    for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADC; irqno++) {
        switch (irqno) {
        case IRQ_EINT4t7:
        case IRQ_EINT8t23:
        case IRQ_UART0:
        case IRQ_UART1:
        case IRQ_UART2:
        case IRQ_ADC:
			irq_set_chip(irqno, &s3c_irq_level_chip);
			irq_set_handler(irqno, handle_level_irq, false);
            break;

        default:
			irq_set_chip(irqno, &s3c_irq_chip);
			irq_set_handler(irqno, handle_edge_irq, false);
			irq_set_flags(irqno, IRQF_VALID);
        }
    }

    /* setup the cascade irq handlers */

    irq_set_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7, true);
    irq_set_handler(IRQ_EINT8t23, s3c_irq_demux_extint8, true);

    irq_set_handler(IRQ_UART0, s3c_irq_demux_uart0, true);
    irq_set_handler(IRQ_UART1, s3c_irq_demux_uart1, true);
    irq_set_handler(IRQ_UART2, s3c_irq_demux_uart2, true);
    irq_set_handler(IRQ_ADC, s3c_irq_demux_adc, true);

    /* external interrupts */

    for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
		irq_set_chip(irqno, &s3c_irq_eint0t3);
		irq_set_handler(irqno, handle_edge_irq);
        set_irq_flags(irqno, IRQF_VALID);
    }

    for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
		irq_set_chip(irqno, &s3c_irqext_chip);
		irq_set_handler(irqno, handle_edge_irq);
        set_irq_flags(irqno, IRQF_VALID);
    }

    /* register the uart interrupts */

    for (irqno = IRQ_RX0; irqno <= IRQ_ERR0; irqno++) {
		irq_set_chip(irqno, &s3c_irq_uart0);
		irq_set_handler(irqno, handle_level_irq);
        set_irq_flags(irqno, IRQF_VALID);
    }

    for (irqno = IRQ_RX1; irqno <= IRQ_ERR1; irqno++) {
		irq_set_chip(irqno, &&s3c_irq_uart1);
		irq_set_handler(irqno, handle_level_irq);
        set_irq_flags(irqno, IRQF_VALID);
    }

    for (irqno = IRQ_RX2; irqno <= IRQ_ERR2; irqno++) {
		irq_set_chip(irqno, &s3c_irq_uart2);
		irq_set_handler(irqno, handle_level_irq);
        set_irq_flags(irqno, IRQF_VALID);
    }

    for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
		irq_set_chip(irqno, &s3c_irq_adc);
		irq_set_handler(irqno, handle_edge_irq);
        set_irq_flags(irqno, IRQF_VALID);
    }
}

